The present invention relates to modeling of electrical circuit characteristics, and more specifically to modeling of an integrated circuit I/O or bi-directional pad cell.
The design of integrated circuits has become increasingly complex as more and more circuits are realizable on a given substrate. This increase in circuit density, and resulting increase in circuit functionality, has resulted in the need for automated circuit design tools. These circuit design tools (hereinafter design test tools) assist a circuit designer in logic entry, simulation and test pattern generation.
Simulation of integrated circuit designs generally rely on models, or other types of information, that the simulator uses to generate signals resulting from some type of circuit stimulus. The relative timings between the stimulus and resulting response are of critical importance as circuits are operated at high speed.
Also of particular importance is how well the simulated responses actually track with the resulting physical implementation of the circuit. This correspondence between predicted and actual responses is important both as to the logical circuit design itself, and to the test patterns that are generated to test the resulting circuit embodiment. Incorrect timings of the logical circuit could result in logical errors being propagated into the physical embodiment of the integrated circuit. Incorrect timings for test patterns could result in test patterns being generated (stimulus and expected response) which don""t match the actual circuit responses during test.
The modeling and simulation of integrated circuit input and output (I/O) pins is particularly troublesome, in that due to the bi-directional nature of many I/O pins (such as those driving and receiving signals on a bus), there can be contentions where more than one driver is trying to drive a given I/O signal to a given (and sometimes conflicting) voltage level. When contention situations exist, the simulation results are erroneous, due to the inability to determine which direction the signal is to be propagated (e.g. into the chip, as driven from some external source, or out of the chip, as driven by the chip circuitry itself).
Current methods of utilizing I/O enable signals for direction determination do not provide actual switch point locations, and do not identify when contention is occurring. These limitations are becoming increasingly important for designs which run at higher frequencies and those which require I/O contention situations to exist.
Enhanced modeling of both internal pull cells and external pull resistors is necessary to improve simulation accuracy as well as to insure that design test tools can extract appropriate test vectors for signals which utilize pull cells/resistors. Incomplete and/or inaccurate pull-up/down information can result in incorrect simulation functionality as well as misplaced strobing (i.e. checking the value) of resistive states. These issues have repeatedly caused manufacturing test problems over the past several years.
Using the combination of the I/O enable signal and the resolved I/O signal for design analysis does not provide enough information to properly handle mid-cycle I/O capabilities and contention situations.
In the case of resistive state modeling, current techniques provide less than accurate simulation information. In some cases, this type of inaccuracy compromises the correctness of the design functionality exhibited during simulation. It also makes strobing of resistive states difficult during manufacturing tests.
It is an object of the present invention to provide an improved circuit model for simulation of electrical circuits.
It is another object of the present invention to provide an improved I/O pad cell model for use by a simulator.
It is yet another object of the present invention to provide accurate timing information in the generation of test patterns for an integrated circuit.
A design system for modeling bi-directional pad cells, the interaction of internal pull cells/resistors with pad cells, and the interaction of external pull cells/resistors with pad cells is provided. A new modeling technique, referred to herein as split-I/O modeling, involves the use of three separate pins on each bi-directional pad cell model: an input-only pin, an output-only pin, and a resolved pin. The input-only pin reflects the data that is supplied to the pad from external sources (strong data that is forced in). The output-only pin reflects the data that is supplied as output from the pad cell (strong data from the output driver). The resolved pin reflects the combination of the input and the output data that are present, as well as the effect of resistive data supplied by pull-up/down resistors/cells (i.e. the resistive state).
The output-only and resolved pins are implemented as internal or hidden pins within a pad cell model. These pins are included in the model for the I/O pad cells in a given library. These pins are named O_ONLY (the output-only pin) and RESOLVED (the resolved pin). The existing pad pin serves as the input-only pin. The system is able to instruct the simulator to log the internal signals through the use of the occurrence name for each I/O pad cell.
The split I/O model provides two modes of operation such that the same model can be used for either chip-level or system-level simulations.